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| www..com W25Q80, W25Q16, W25Q32 8M-BIT, 16M-BIT AND 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI -1- Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 Table of Contents 1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION ......................................................................................................... 5 FEATURES ................................................................................................................................. 5 PIN CONFIGURATION SOIC 208-MIL....................................................................................... 6 PAD CONFIGURATION WSON 6X5-MM .................................................................................. 6 PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM........................................................ 6 PIN CONFIGURATION SOIC 300-MIL....................................................................................... 7 PIN DESCRIPTION SOIC 300-MIL ............................................................................................ 7 7.1 7.2 7.3 7.4 7.5 7.6 8. 9. Package Types ............................................................................................................... 8 Chip Select (/CS) ............................................................................................................ 8 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .............................. 8 Write Protect (/WP)......................................................................................................... 8 HOLD (/HOLD) ............................................................................................................... 8 Serial Clock (CLK) .......................................................................................................... 8 BLOCK DIAGRAM ...................................................................................................................... 9 FUNCTIONAL DESCRIPTION ................................................................................................. 10 9.1 SPI OPERATIONS ....................................................................................................... 10 9.1.1 9.1.2 9.1.3 9.1.4 Standard SPI Instructions...............................................................................................10 Dual SPI Instructions ......................................................................................................10 Quad SPI Instructions.....................................................................................................10 Hold Function .................................................................................................................10 Write Protect Features....................................................................................................11 9.2 10. WRITE PROTECTION.................................................................................................. 11 9.2.1 CONTROL AND STATUS REGISTERS................................................................................... 12 10.1 STATUS REGISTER .................................................................................................... 12 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.7 10.1.8 BUSY............................................................................................................................12 Write Enable Latch (WEL) ............................................................................................12 Block Protect Bits (BP2, BP1, BP0)..............................................................................12 Top/Bottom Block Protect (TB).....................................................................................12 Sector/Block Protect (SEC) ..........................................................................................12 Status Register Protect (SRP1, SRP0).........................................................................13 Quad Enable (QE) ........................................................................................................13 Status Register Memory Protection ..............................................................................15 Manufacturer and Device Identification ........................................................................18 Instruction Set Table 1..................................................................................................19 Instruction Set Table 2 (Read Instructions) ..................................................................20 10.2 INSTRUCTIONS........................................................................................................... 18 10.2.1 10.2.2 10.2.3 -2- www..com W25Q80, W25Q16, W25Q32 10.2.4 10.2.5 10.2.6 10.2.7 10.2.8 10.2.9 10.2.10 10.2.11 10.2.12 10.2.13 10.2.14 10.2.15 10.2.16 10.2.17 10.2.18 10.2.19 10.2.20 10.2.21 10.2.22 10.2.23 10.2.24 10.2.25 10.2.26 10.2.27 10.2.28 Write Enable (06h)........................................................................................................21 Write Disable (04h).......................................................................................................21 Read Status Register-1 (05h) and Read Status Register-2 (35h).................................22 Write Status Register (01h) ..........................................................................................23 Read Data (03h) ...........................................................................................................24 Fast Read (0Bh) ...........................................................................................................25 Fast Read Dual Output (3Bh) .....................................................................................26 Fast Read Quad Output (6Bh)....................................................................................27 Fast Read Dual I/O (BBh)...........................................................................................28 Fast Read Quad I/O (EBh) .........................................................................................30 Page Program (02h) ...................................................................................................32 Quad Input Page Program (32h) ................................................................................33 Sector Erase (20h) .....................................................................................................34 32KB Block Erase (52h) .............................................................................................35 64KB Block Erase (D8h).............................................................................................36 Chip Erase (C7h / 60h)...............................................................................................37 Erase Suspend (75h)..................................................................................................38 Erase Resume (7Ah) ..................................................................................................38 Power-down (B9h) ......................................................................................................39 High Performance Mode (A3h) ...................................................................................40 Release Power-down or High Performance Mode / Device ID (ABh) .........................40 Read Manufacturer / Device ID (90h) .........................................................................42 Read Unique ID Number ............................................................................................43 JEDEC ID (9Fh) .........................................................................................................44 Mode Bit Reset (FFh or FFFFh) .................................................................................45 11. ELECTRICAL CHARACTERISTICS (PRELIMINARY)............................................................. 46 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 Absolute Maximum Ratings .......................................................................................... 46 Operating Ranges......................................................................................................... 46 Endurance and Data Retention .................................................................................... 47 Power-up Timing and Write Inhibit Threshold .............................................................. 47 DC Electrical Characteristics ........................................................................................ 48 AC Measurement Conditions........................................................................................ 49 AC Electrical Characteristics ........................................................................................ 50 AC Electrical Characteristics (cont'd) ........................................................................... 51 Serial Output Timing ..................................................................................................... 52 Input Timing................................................................................................................. 52 Hold Timing ................................................................................................................. 52 12. PACKAGE SPECIFICATION .................................................................................................... 53 -3- Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 12.1 12.2 12.3 12.4 12.5 13. 14. 13.1 8-Pin SOIC 208-mil (Package Code SS)...................................................................... 53 8-Pin PDIP 300-mil (Package Code DA) ...................................................................... 54 8-contact 6x5 WSON (Package Code ZP) ................................................................... 55 8-contact 6x5 WSON Cont'd. ....................................................................................... 56 16-Pin SOIC 300-mil (Package Code SF) .................................................................... 57 Valid Part Numbers and Top Side Marking .................................................................. 59 ORDERING INFORMATION .................................................................................................... 58 REVISION HISTORY ................................................................................................................ 60 -4- www..com W25Q80, W25Q16, W25Q32 1. GENERAL DESCRIPTION The W25Q80 (8M-bit), W25Q16 (16M-bit), and W25Q32 (32M-bit) Serial Flash memories provide a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 5mA active and 1A for power-down. All devices are offered in space-saving packages. The W25Q80/16/32 array is organized into 4,096/8,192/16,384 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time using the Page Program instructions. Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q80/16/32 has 256/512/1024 erasable sectors and 16/32/64 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q80/16/32 supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI using SPI pins: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using the Fast Read Dual/Quad Output instructions. These transfer rates are comparable to those of 8 and 16-bit Parallel Flash memories. A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number. 2. FEATURES * Family of SpiFlash Memories - W25Q80: 8M-bit / 1M -byte (1,048,576) - W25Q16: 16M-bit / 2M-byte (2,097,152) - W25Q32: 32M-bit / 4M-byte (4,194,304) - 256-bytes per programmable page * Standard, Dual or Quad SPI - Standard SPI: CLK, /CS, DI, DO, /WP, /Hold - Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold - Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 * Highest Performance Serial Flash - Up to 6X that of ordinary Serial Flash - 80MHz clock operation - 160MHz equivalent Dual SPI - 320MHz equivalent Quad SPI - 40MB/S continuous data transfer rate - 30MB/S random access (32-byte fetch) - Comparable to X16 Parallel Flash * Low Power, Wide Temperature Range - Single 2.7 to 3.6V supply - 4mA active current, <1A Power-down (typ.) - -40C to +85C operating range * Flexible Architecture with 4KB sectors - Uniform Sector Erase (4K-bytes) - Block Erase (32K and 64K-bytes) - Program one to 256 bytes - Up to 100,000 erase/write cycles - 20-year data retention * Advanced Security Features - Software and Hardware Write-Protect - Top or Bottom, Sector or Block selection (1) - Lock-Down and OTP protection - 64-Bit Unique ID for each device(1) Note 1: These features are on special order. Please contact Winbond for details. * Space Efficient Packaging - 8-pin SOIC 208-mil - 8-pad WSON 6x5-mm (W25Q80 & W25Q16) -16-pin SOIC 300-mil (W25Q16 & W25Q32) -5- Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 3. PIN CONFIGURATION SOIC 208-MIL Figure 1a. W25Q80, W25Q16, W25Q32 Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 4. PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25Q80, W25Q16 Pad Assignments, 8-pad WSON (Package Code ZP) 5. PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM PIN NO. 1 2 3 4 5 6 7 8 PIN NAME /CS DO (IO1) /WP (IO2) GND DI (IO0) CLK /HOLD (IO3) VCC I/O I I/O I/O I/O I I/O Chip Select Input FUNCTION Data Output (Data Input Output 1)*1 Write Protect Input ( Data Input Output 2)*2 Ground Data Input (Data Input Output 0)*1 Serial Clock Input Hold Input (Data Input Output 3)*2 Power Supply *1 IO0 and IO1 are used for Dual and Quad instructions *2 IO0 - IO3 are used for Quad instructions -6- www..com W25Q80, W25Q16, W25Q32 6. PIN CONFIGURATION SOIC 300-MIL Figure 1c. W25Q16 and W25Q32 Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 7. PIN DESCRIPTION SOIC 300-MIL PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PAD NAME /HOLD (IO3) VCC N/C N/C N/C N/C /CS DO (IO1) /WP (IO2) GND N/C N/C N/C N/C DI (IO0) CLK I/O I/O Power Supply No Connect No Connect No Connect No Connect I I/O I/O Chip Select Input FUNCTION Hold Input (Data Input Output 3)*2 Data Output (Data Input Output 1)*1 Write Protect Input (Data Input Output 2)*2 Ground No Connect No Connect No Connect No Connect I/O I Data Input (Data Input Output 0)*1 Serial Clock Input *1 IO0 and IO1 are used for Dual and Quad instructions *2 IO0 - IO3 are used for Quad instructions Publication Release Date: September 26, 2007 Preliminary - Revision B -7- www..com W25Q80, W25Q16, W25Q32 7.1 Package Types W25Q80 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 6x5-mm WSON (package code ZP). W25Q16 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 6x5-mm WSON as shown in figure 1a, and 1b, respectively. The W25Q16 and W25Q32 are offered in a 16-pin plastic 300-mil width SOIC (package code SF) as shown in figure 1c. Package diagrams and dimensions are illustrated at the end of this datasheet. 7.2 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up (see "Write Protection" and figure 30). If needed a pull-up resister on /CS can be used to accomplish this. 7.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) The W25Q80/16/32 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge CLK. Dual and Quad SPI instruction use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1 the /WP pin becomes IO2 and /HOLD pin becomes IO3. 7.4 Write Protect (/WP) The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register's Block Protect (SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin (Hardware Write Protect) function is not available since this pin is used for IO2. See figure 1a, 1b, and 1c for the pin configuration of Quad I/O operation. 7.5 HOLD (/HOLD) The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don't care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See figure 1a, 1b, and 1c for the pin configuration of Quad I/O operation. 7.6 Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations") -8- www..com W25Q80, W25Q16, W25Q32 8. BLOCK DIAGRAM Figure 2. W25Q80, W25Q16 and W25Q32 Block Diagram -9- Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 9. FUNCTIONAL DESCRIPTION 9.1 SPI OPERATIONS 9.1.1 Standard SPI Instructions The W25Q80/16/32 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge CLK. SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3 the CLK signal is normally high on the falling and rising edges of /CS. 9.1.2 Dual SPI Instructions The W25Q80/16/32 supports Dual SPI operation when using the "Fast Read Dual Output and Dual I/O" (3B and BB hex) instructions. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions the DI and DO pins become bidirectional I/O pins; IO0 and IO1. 9.1.3 Quad SPI Instructions The W25Q80/16/32 supports Quad SPI operation when using the "Fast Read Quad Output and Fast Read Quad I/O" (6B and EB hex respectively). These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. 9.1.4 Hold Function The /HOLD signal allows the W25Q80/16/32 operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not during Quad SPI. To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the - 10 - www..com W25Q80, W25Q16, W25Q32 /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device. 9.2 WRITE PROTECTION Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the W25Q80/16/32 provides several means to protect data from inadvertent writes. 9.2.1 * * * * * * * Write Protect Features Device resets when VCC is below threshold Time delay write disable after Power-up Write enable/disable instructions and automatic write disable after program and erase Software and Hardware (/WP pin) write protection using Status Register Write Protection using Power-down instruction Lock Down write protection until next power-up(1) One Time Program (OTP) write protection(1) Note 1: These features are available upon special order. Please contact Winbond for details. Upon power-up or at power-down the W25Q80/16/32 will maintain a reset condition while VCC is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 29). While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a writedisabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP0, SRP1) and Block Protect (SEC,TB, BP2, BP1 and BP0) bits. These settings allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction. Publication Release Date: September 26, 2007 Preliminary - Revision B - 11 - www..com W25Q80, W25Q16, W25Q32 10. CONTROL AND STATUS REGISTERS The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection and the Quad SPI setting. The Write Status Register instruction can be used to configure the devices write protection features and Quad SPI setting. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and in some cases the /WP pin. 10.1 STATUS REGISTER 10.1.1 BUSY BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase Suspend instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions. 10.1.2 Write Enable Latch (WEL) Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register. 10.1.3 Block Protect Bits (BP2, BP1, BP0) The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected. 10.1.4 Top/Bottom Block Protect (TB) The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits. 10.1.5 Sector/Block Protect (SEC) The non-volatile Sector protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0. - 12 - www..com W25Q80, W25Q16, W25Q32 10.1.6 Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 0 0 0 1 1 SRP0 0 1 1 0 1 /WP X 0 1 X X Status Register Software Protection Hardware Protected Hardware Unprotected Power Supply Lock-Down(1) One Time Program(1) Description /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default] When /WP pin is low the Status Register locked and can not be written to. When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. Status Register is protected and can not be written to again until the next power-down, power-up cycle.(2) Status Register is permanently protected and can not be written to. Note: 1. These features are available upon special order. Please contact Winbond for details. 2. When SRP1, SRP0 = (1,0), a power-down, power-up cycle will change SRP1, SRP0 to (0,0) state. 10.1.7 Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad operation. When the QE bit is set to a 0 state (factory default) the /WP pin and /Hold are enabled. When the QE pin is set to a 1 the Quad IO2 and IO3 pins are enabled. WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins are tied directly to the power supply or ground. - 13 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 Figure 3a. Status Register-1 Figure 3b. Status Register-2 - 14 - www..com W25Q80, W25Q16, W25Q32 10.1.8 Status Register Memory Protection STATUS REGISTER(1) SEC TB BP2 BP1 BP0 BLOCK(S) W25Q32 (32M-BIT) MEMORY PROTECTION ADDRESSES DENSITY PORTION X 0 0 0 0 0 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 1 X 0 0 0 0 0 0 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 X 1 0 1 X NONE 63 62 and 63 60 thru 63 56 thru 63 48 thru 63 32 thru 63 0 0 and 1 0 thru 3 0 thru 7 0 thru 15 0 thru 31 0 thru 63 63 63 63 63 0 0 0 0 NONE 3F0000h - 3FFFFFh 3E0000h - 3FFFFFh 3C0000h - 3FFFFFh 380000h - 3FFFFFh 300000h - 3FFFFFh 200000h - 3FFFFFh 000000h - 00FFFFh 000000h - 01FFFFh 000000h - 03FFFFh 000000h - 07FFFFh 000000h - 0FFFFFh 000000h - 1FFFFFh 000000h - 3FFFFFh 3FF000h - 3FFFFFh 3FE000h - 3FFFFFh 3FC000h - 3FFFFFh 3F8000h - 3FFFFFh 000000h - 000FFFh 000000h - 001FFFh 000000h - 003FFFh 000000h - 007FFFh NONE 64KB 128KB 256KB 512KB 1MB 2MB 64KB 128KB 256KB 512KB 1MB 2MB 4MB 4KB 8KB 16KB 32KB 4KB 8KB 16KB 32KB NONE Upper 1/64 Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 Lower 1/64 Lower 1/32 Lower 1/16 Lower 1/8 Lower 1/4 Lower 1/2 ALL Top Block Top Block Top Block Top Block Bottom Block Bottom Block Bottom Block Bottom Block - 15 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 STATUS REGISTER(1) SEC TB BP2 BP1 BP0 BLOCK(S) W25Q16 (16M-BIT) MEMORY PROTECTION ADDRESSES DENSITY PORTION X 0 0 0 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 1 X 0 0 0 0 0 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 1 0 1 0 1 X 1 0 1 X 1 0 1 X NONE 31 30 and 31 28 thru 31 24 thru 31 16 thru 31 0 0 and 1 0 thru 3 0 thru 7 0 thru 15 0 thru 31 31 31 31 31 0 0 0 0 NONE 1F0000h - 1FFFFFh 1E0000h - 1FFFFFh 1C0000h - 1FFFFFh 180000h - 1FFFFFh 100000h - 1FFFFFh 000000h - 00FFFFh 000000h - 01FFFFh 000000h - 03FFFFh 000000h - 07FFFFh 000000h - 0FFFFFh 000000h - 1FFFFFh 1FF000h - 1FFFFFh 1FE000h - 1FFFFFh 1FC000h - 1FFFFFh 1F8000h - 1FFFFFh 000000h - 000FFFh 000000h - 001FFFh 000000h - 003FFFh 000000h - 007FFFh NONE 64KB 128KB 256KB 512KB 1MB 64KB 128KB 256KB 512KB 1MB 2MB 4KB 8KB 16KB 32KB 4KB 8KB 16KB 32KB NONE Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 Lower 1/32 Lower 1/16 Lower 1/8 Lower 1/4 Lower 1/2 ALL Top Block Top Block Top Block Top Block Bottom Block Bottom Block Bottom Block Bottom Block - 16 - www..com W25Q80, W25Q16, W25Q32 STATUS REGISTER(1) SEC TB BP2 BP1 BP0 W25Q80 (8M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES DENSITY PORTION X 0 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 X 1 0 1 X 1 0 1 X NONE 15 14 and 15 12 thru 15 8 thru 15 0 0 and 1 0 thru 3 0 thru 7 0 thru 15 15 15 15 15 0 0 0 0 NONE 0F0000h - 0FFFFFh 0E0000h - 0FFFFFh 0C0000h - 0FFFFFh 080000h - 0FFFFFh 000000h - 00FFFFh 000000h - 01FFFFh 000000h - 03FFFFh 000000h - 07FFFFh 000000h - 0FFFFFh 0FF000h - 0FFFFFh 0FE000h - 0FFFFFh 0FC000h - 0FFFFFh 0F8000h - 0FFFFFh 000000h - 000FFFh 000000h - 001FFFh 000000h - 003FFFh 000000h - 007FFFh NONE 64KB 128KB 256KB 512KB 64KB 128KB 256KB 512KB 1MB 4KB 8KB 16KB 32KB 4KB 8KB 16KB 32KB NONE Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 Lower 1/16 Lower 1/8 Lower 1/4 Lower 1/2 ALL Top Block Top Block Top Block Top Block Bottom Block Bottom Block Bottom Block Bottom Block Note: 1. x = don't care - 17 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2 INSTRUCTIONS The instruction set of the W25Q80/16/32 consists of fifteen basic instructions that are fully controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don't care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in figures 4 through 19. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed. 10.2.1 Manufacturer and Device Identification MANUFACTURER ID (M7-M0) EFh Winbond Serial Flash Device ID Instruction W25Q80 W25Q16 W25Q32 (ID7-ID0) ABh, 90h 13h 14h 15h (ID15-ID0) 9Fh 4014h 4015h 4016h - 18 - www..com W25Q80, W25Q16, W25Q32 10.2.2 Instruction Set Table 1 (1) INSTRUCTION NAME Write Enable Write Disable Read Status Register-1 Read Status Register-2 Write Status Register Page Program Quad Page Program Block Erase (64KB) Block Erase (32KB) Sector Erase (4KB) Chip Erase Erase Suspend Erase Resume Power-down High Performance Mode Mode Bit Reset (4) BYTE 1 (CODE) 06h 04h 05h 35h 01h 02h 32h D8h 52h 20h C7h/60h 75h 7Ah B9h A3h FFh ABh 90h BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 (S7-S0) (S15-S8) (2) (2) (S7-S0) A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 (S15-S8) A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 (D7-D0) (D7-D0, ...) (3) dummy FFh dummy dummy dummy (M7-M0) Manufacturer dummy dummy Release Power down or HPM / Device ID Manufacturer/ Device ID (6) dummy dummy dummy (ID15-ID8) Memory Type dummy 00h dummy (ID7-ID0) Capacity (ID7-ID0) (5) (M7-M0) Dummy (ID7-ID0) (ID63-ID0) Read Unique ID JEDEC ID (7) 4Bh 9Fh Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis "()" indicate data being read from the device on the DO pin. 2. The Status Register contents will repeat continuously until /CS terminates the instruction. 3. Quad Page Program Input Data IO0 = (D4, D0, ......) IO1 = (D5, D1, ......) IO2 = (D6, D2, ......) IO3 = (D7, D3, ......) 4. This instruction is recommended when using the Dual or Quad Mode bit feature. See section 10.2.28 for more information. 5. The Device ID will repeat continuously until /CS terminates the instruction. 6. See Manufacturer and Device Identification table for Device ID information. 7. This feature is available upon special order. Please contact Winbond for details. - 19 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.3 Instruction Set Table 2 (Read Instructions) INSTRUCTION NAME Read Data Fast Read Fast Read Dual Output Fast Read Dual I/O Fast Read Quad Output Fast Read Quad I/O BYTE 1 (CODE) 03h 0Bh 3Bh BBh 6Bh EBh BYTE 2 A23-A16 A23-A16 A23-A16 A23-A8 (2) BYTE 3 A15-A8 A15-A8 A15-A8 A7-A0, M7-M0 A15-A8 (4) (2) BYTE 4 A7-A0 A7-A0 A7-A0 (D7-D0, ...) A7-A0 (5) (1) BYTE 5 (D7-D0) dummy dummy BYTE 6 (D7-D0) (D7-D0, ...) (1) A23-A16 A23-A0, M7-M0 dummy (3) (D7-D0, ...) (3) (x,x,x,x, D7-D0, ...) (D7-D0, ...) Notes: 1: Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2: Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 3: Quad Output Data IO0 = (D4, D0, .....) IO1 = (D5, D1, .....) IO2 = (D6, D2, .....) IO3 = (D7, D3, .....) 4: Quad Input Address IO0 = A20, A16, A12, A8 , A4, A0, M4, M0 IO1 = A21, A17, A13, A9 , A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5: Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0, .....) IO1 = (x, x, x, x, D5, D1, .....) IO2 = (x, x, x, x, D6, D2, .....) IO3 = (x, x, x, x, D7, D3, .....) - 20 - www..com W25Q80, W25Q16, W25Q32 10.2.4 Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code "06h" into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. Figure 4. Write Enable Instruction Sequence Diagram 10.2.5 Write Disable (04h) The Write Disable instruction (Figure 5) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code "04h" into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 5. Write Disable Instruction Sequence Diagram - 21 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.6 Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code "05h" for Status Register-1 and "35h" for Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in figure 6. The Status Register bits are shown in figure 3a and 3b and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0, SRP1 and QE bits (see description of the Status Register earlier in this datasheet). The Status Register instruction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 6. The instruction is completed by driving /CS high. Figure 6. Read Status Register Instruction Sequence Diagram - 22 - www..com W25Q80, W25Q16, W25Q32 10.2.7 Write Status Register (01h) The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction must previously have been executed for the device to accept the Write Status Register Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code "01h", and then writing the status register data byte as illustrated in figure 7. The Status Register bits are shown in figure 3 and described earlier in this datasheet. Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7, 5, 4, 3, 2 of Status Register-1) and QE, SRP1(bits 9 and 8 of Status Register-2) can be written to. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. The /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be executed. If /CS is driven high after the eighth clock (compatible with the 25X series) the QE and SRP1 bits will be cleared to 0. After /CS is driven high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Register cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. The Write Status Register instruction allows the Block Protect bits (SEC, TB, BP2, BP1 and BP0) to be set for protecting all, a portion, or none of the memory from erase and program instructions. Protected areas become read-only (see Status Register Memory Protection table and description). The Write Status Register instruction also allows the Status Register Protect bits (SRP0, SRP1) to be set. Those bits are used in conjunction with the Write Protect (/WP) pin, Lock out or OTP features to disable writes to the status register. Please refer to 10.1.16 for detailed descriptions regarding Status Register protection methods. Factory default for all status Register bits are 0. Figure 7. Write Status Register Instruction Sequence Diagram - 23 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.8 Read Data (03h) The Read Data instruction allows one more data bytes to be sequentially read from the memory. The instruction is initiated by driving the /CS pin low and then shifting the instruction code "03h" followed by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. The Read Data instruction sequence is shown in figure 8. If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR (see AC Electrical Characteristics). Figure 8. Read Data Instruction Sequence Diagram - 24 - www..com W25Q80, W25Q16, W25Q32 10.2.9 Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24-bit address as shown in figure 9. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a "don't care". Figure 9. Fast Read Instruction Sequence Diagram - 25 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.10 Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO0 and IO1. This allows data to be transferred from the W25Q80/16/32 at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache codesegments to RAM for execution. Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is "don't care". However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock. Figure 10. Fast Read Dual Output Instruction Sequence Diagram - 26 - www..com W25Q80, W25Q16, W25Q32 10.2.11 Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the W25Q80/16/32 at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24-bit address as shown in figure 11. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is "don't care". However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. Figure 11. Fast Read Quad Output Instruction Sequence Diagram - 27 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.12 Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. To ensure optimum performance the High Performance Mode (HPM) instruction (A3h) must be executed once, prior to the Fast Read Dual I/O Instruction. The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the Mode bits (M7-0) after the input Address bits (A23-0), as shown in figure 12a. The upper nibble of the Mode (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0) are don't care ("x"). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the Mode bits (M7-0) equals "Ax" hex, then the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BBh instruction code, as shown in figure 12b.. This reduces the instruction sequence by eight clocks and allows the address to be immediately entered after /CS is asserted low. If the Mode bits (M7-0) are any value other than "Ax" hex, the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A Mode Bit Reset instruction can be used to reset Mode Bits (M7-0) before issuing normal instructions (See 10.2.28 for detailed descriptions). Figure 12a. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh) - 28 - www..com W25Q80, W25Q16, W25Q32 Figure 12b. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = Axh) - 29 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.13 Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clock are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast read Quad I/O Instruction. To ensure optimum performance the High Performance Mode (HPM) instruction (A3h) must be executed once, prior to the Fast Read Quad I/O Instruction. The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the Mode bits (M7-0) after the input Address bits (A23-0), as shown in figure 13a. The upper nibble of the Mode (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0) are don't care ("x"). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the Mode bits (M7-0) equals "Ax" hex, then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh instruction code, as shown in figure 13b. This reduces the instruction sequence by eight clocks and allows the address to be immediately entered after /CS is asserted low. If the Mode bits (M7-0) are any value other than "Ax" hex, the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A Mode Bit Reset instruction can be used to reset Mode Bits (M7-0) before issuing normal instructions (See 10.2.28 for detailed descriptions). Figure 13a. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh) - 30 - www..com W25Q80, W25Q16, W25Q32 Figure 13b. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = Axh) - 31 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.14 Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code "02h" followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in figure 14. If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits. Figure 14. Page Program Instruction Sequence Diagram - 32 - www..com W25Q80, W25Q16, W25Q32 10.2.15 Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater than the time it take to clock-in the data. To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable instruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code "32h" followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. All other functions of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in figure 15. Figure 15. Quad Input Page Program Instruction Sequence Diagram - 33 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.16 Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "20h" followed a 24-bit sector address (A23-A0) (see Figure 2). The Sector Erase instruction sequence is shown in figure 16. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 16. Sector Erase Instruction Sequence Diagram - 34 - www..com W25Q80, W25Q16, W25Q32 10.2.17 32KB Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "52h" followed a 24-bit block address (A23-A0) (see Figure 2). The Block Erase instruction sequence is shown in figure 17. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 17. 32KB Block Erase Instruction Sequence Diagram Note: For W25Q16, user should not issue 32KB Block Erase (52h) instruction to the top or bottom 32KB block when SEC bit in Status Register is set to "1". - 35 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.18 64KB Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "D8h" followed a 24-bit block address (A23-A0) (see Figure 2). The Block Erase instruction sequence is shown in figure 18. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 18. 64KB Block Erase Instruction Sequence Diagram Note: For W25Q16, user should not issue 64KB Block Erase (D8h) instruction to the top or bottom 64KB block when SEC bit in Status Register is set to "1". - 36 - www..com W25Q80, W25Q16, W25Q32 10.2.19 Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "C7h" or "60h". The Chip Erase instruction sequence is shown in figure 19. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 19. Chip Erase Instruction Sequence Diagram - 37 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.20 Erase Suspend (75h) The Erase Suspend instruction "75h", allows the system to interrupt a sector or block erase operation and then read from or program data to, any other sector or block. The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8, C7h, 60h ) are not allowed during suspend. Erase Suspend is valid only during the sector or block erase operation. If written during the chip erase or program operation, the Erase Suspend instruction is ignored. A maximum of time of "tsus" (See AC Characteristics) is required to suspend the erase operation. The BUSY bit in the Status register will clear to 0 after Erase Suspend. Figure 20. Erase Suspend Instruction Sequence 10.2.21 Erase Resume (7Ah) The Erase Resume instruction must be written to resume the sector or block erase operation after an Erase Suspend. After issued the BUSY bit in the status register will be set to a 1 and the sector or block will complete the erase operation. Resume instructions will be ignored unless an Erase Suspend operation is active. Figure 21. Erase Resume Instruction Sequence - 38 - www..com W25Q80, W25Q16, W25Q32 10.2.22 Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code "B9h" as shown in figure 22. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Powerdown instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP (See AC Characteristics). While in the power-down state only the Release from Power-down / Device ID instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 22. Deep Power-down Instruction Sequence Diagram - 39 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.23 High Performance Mode (A3h) The High Performance Mode (HPM) instruction must be executed prior to Dual or Quad I/O instructions when operating at high frequencies (see FR and FR1 in AC Electrical Characteristics). This instruction allows pre-charging of internal charge pumps so the voltages required for accessing the Flash memory array are readily available. The instruction sequence includes the A3h instruction code followed by three dummy byte clocks shown in Fig. 23. (Contact Winbond for the latest 25Q data sheet with updated HPM diagram). After the HPM instruction is executed, the device will maintain a slightly higher standby current (Icc3) than standard SPI operation. The Release from Power-down or HPM instruction (ABh) can be used to return to standard SPI standby current (Icc1). Figure 23. High Performance Mode Instruction Sequence 10.2.24 Release Power-down or High Performance Mode / Device ID (ABh) The Release from Power-down or High performance Mode / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state or High Performance Mode, or obtain the devices electronic identification (ID) number. To release the device from the power-down state or High Performance Mode, the instruction is issued by driving the /CS pin low, shifting the instruction code "ABh" and driving /CS high as shown in figure 24. Release from power-down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code "ABh" followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 25. The Device ID values for the W25Q80, W25Q16, and W25Q32 are listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. - 40 - www..com W25Q80, W25Q16, W25Q32 When used to release the device from the power-down state and obtain the Device ID, the instruction is the same as previously described, and shown in figure 25, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instructions will be accepted. If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle Figure 24. Release Power-down/High Performance Mode Instruction Sequence Figure 25. Release Power-down / Device ID Instruction Sequence Diagram - 41 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.25 Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code "90h" followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 26. The Device ID values for the W25Q80, W25Q16, and W25Q32 are listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. Figure 26. Read Manufacturer / Device ID Diagram - 42 - www..com W25Q80, W25Q16, W25Q32 10.2.26 Read Unique ID Number(1) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q80, W25Q16 or W25Q64 device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code "4Bh" followed by a four bytes of dummy clocks. After which, the 64-bit ID is shifted out on the falling edge of CLK as shown in figure 27. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 101 102 103 Figure 27. Read Unique ID Number Instruction Sequence Note: 1. For W25Q16, this feature is available upon special request. Please contact Winbond for details. - 43 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 10.2.27 JEDEC ID (9Fh) For compatibility reasons, the W25Q80/16/32 provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code "9Fh". The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 28. For memory type and capacity values refer to Manufacturer and Device Identification table. Figure 28. Read JEDEC ID - 44 - www..com W25Q80, W25Q16, W25Q32 10.2.28 Mode Bit Reset (FFh or FFFFh) For Fast Read Dual/Quad I/O operations, Mode Bits (M7-0) are implemented to further reduce instruction overhead. By setting the Mode Bits (M7-0) to "Ax" hex, the next Fast Read Dual/Quad I/O operation does not require the BBh/EBh instruction code (See 10.2.12 Fast Read Dual I/O and 10.2.13 Fast Read Quad I/O for detail descriptions). If the system controller is Reset during operation it will likely send a standard SPI instruction, such as Read ID (9Fh) or Fast Read (0Bh), to the 25Q16/32/80. However, as with most SPI Serial Flash memories, the 25Q80/16/32 does not have a hardware Reset pin, so if Mode bits are set to "Ax" hex, the 25Q80/16/32 will not recognize any standard SPI instructions. To address this possibility, it is recommended to issue a Mode Bit Reset instruction as the first instruction after a system Reset. Doing so will release the Mode Bits for the "Ax" hex state and allow Standard SPI instructions to be recognized. The Mode Bits Reset instruction is shown in figure 29. Mode Bit Reset for Quad I/O Mode Bit Reset for Dual I/O /CS Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3 Mode 0 CLK IO0 IO1 IO2 IO3 Mode 0 FFh FFh Don't Care Don't Care Don't Care Figure 29. Mode Bit Reset for Fast Read Dual/Quad I/O To reset Mode Bit during Quad I/O operation, only eight clocks are needed. The instruction is "FFh". To reset Mode Bit during Dual I/O operation, sixteen clocks are needed to shift in instruction "FFFFh". - 45 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 11. ELECTRICAL CHARACTERISTICS (PRELIMINARY) (4) 11.1 Absolute Maximum Ratings (1) PARAMETERS SYMBOL CONDITIONS RANGE UNIT Supply Voltage Voltage Applied to Any Pin Transient Voltage on any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: VCC VIO VIOT TSTG TLEAD VESD Human Body Model(3) Relative to Ground <20nS Transient Relative to Ground -0.6 to +4.0 -0.6 to VCC+0.4 -2.0V to VCC+2.0V -65 to +150 See Note (2) -2000 to +2000 V V V C C V 1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU. 3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms). 4. See preliminary designation at the end of this datasheet. 11.2 Operating Ranges PARAMETER SYMBOL CONDITIONS SPEC MIN MAX UNIT Supply Voltage(1) Ambient Temperature, Operating Note: 1. VCC TA FR = 80MHz, fR = 50MHz Commercial Industrial 2.7 0 -40 3.6 +70 +85 V C VCC voltage during Read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage. - 46 - www..com W25Q80, W25Q16, W25Q32 11.3 Endurance and Data Retention PARAMETER CONDITIONS MIN MAX UNIT Erase/Program Cycles Data Retention 4KB sector, 32/64KB block or full chip. 55C 100,000 20 cycles years 11.4 Power-up Timing and Write Inhibit Threshold PARAMETER SYMBOL SPEC MIN MAX UNIT VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. tVSL(1) tPUW(1) VWI(1) 10 1 1 10 2 s ms V Figure 30. Power-up Timing and Voltage Levels - 47 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 11.5 DC Electrical Characteristics PARAMETER Input Capacitance Output Capacitance Input Leakage I/O Leakage Standby Current Power-down Current High performance current Current Read Data / Dual /Quad 1MHz(2) Current Read Data / Dual /Quad 33MHz(2) Current Read Data / Dual /Quad 50MHz(2) Current Read Data / Dual Output Read/Quad Output Read 80MHz(2) Current Write Status Register Current Page Program Current Sector/Block Erase Current Chip Erase Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Notes: 1. Tested on sample basis and specified through design and characterization data. TA=25 C, VCC 3V. 2. Checker Board Pattern. SYMBOL CIN(1) Cout(1) ILI ILO ICC1 ICC2 ICC3 ICC4 ICC4 ICC4 ICC4 ICC6 ICC7 ICC8 ICC9 VIL VIH VOL VOH CONDITIONS VIN = 0V(2) VOUT = 0V(2) SPEC MIN TYP MAX 6 8 2 2 UNIT pF pF A A A A A mA mA mA mA mA mA mA mA V V V V /CS = VCC, VIN = GND or VCC /CS = VCC, VIN = GND or VCC After enable High Performance mode C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open /CS = VCC /CS = VCC /CS = VCC /CS = VCC 25 1 50 4/5/6 6/7/8 7/8/9 10/11/12 8 20 20 20 -0.5 VCC x 0.7 50 5 100 6/7.5/9 9/10.5/12 10/12/13.5 15/16.5/18 12 25 25 25 VCC x 0.3 VCC + 0.4 0.4 IOL = 1.6 mA IOH = -100 A VCC - 0.2 - 48 - www..com W25Q80, W25Q16, W25Q32 11.6 AC Measurement Conditions PARAMETER SYMBOL SPEC MIN MAX UNIT Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: CL TR, TF VIN IN 30 5 0.2 VCC to 0.8 VCC 0.3 VCC to 0.7 VCC 0.5 VCC to 0.5 VCC pF ns V V V OUT 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 31. AC Measurement I/O Waveform - 49 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 11.7 AC Electrical Characteristics DESCRIPTION SYMBOL ALT MIN SPEC TYP MAX UNIT Clock frequency for all instructions, except Read Data (03h) 2.7V-3.6V VCC & Industrial Temperature Clock freq. Read Data instruction (03h) Clock High, Low Time except Read Data (03h) Clock High, Low Time for Read Data (03h) instruction Clock Rise Time peak to peak Clock Fall Time peak to peak /CS Active Setup Time relative to CLK /CS Not Active Hold Time relative to CLK Data In Setup Time Data In Hold Time /CS Active Hold Time relative to CLK /CS Not Active Setup Time relative to CLK /CS Deselect Time (for Array Read Array Read / Erase or Program Read Status Registers) Output Disable Time Clock Low to Output Valid 2.7V-3.6V / 3.0V-3.6V Clock Low to Output Valid (for Read ID instructions) 2.7V-3.6V / 3.0V-3.6V Output Hold Time /HOLD Active Setup Time relative to CLK FR fR tCLH, tCLL(1) tCRLH, tCRLL(1) tCLCH(2) tCHCL(2) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(2) tCLQV1 fC D.C. D.C. 6/7 8 0.1 0.1 80 50 MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns tCSS 5 5 tDSU tDH 2 5 5 5 tCSH tDIS tV1 10/5 0 7 7/6 ns ns tCLQV2 tCLQX tHLCH tV2 tHO 0 5 8.5 / 7.5 ns ns ns Continued - next page - 50 - www..com W25Q80, W25Q16, W25Q32 11.8 AC Electrical Characteristics (cont'd) DESCRIPTION SYMBOL ALT MIN SPEC TYP MAX UNIT /HOLD Active Hold Time relative to CLK /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z /HOLD to Output High-Z Write Protect Setup Time Before /CS Low Write Protect Hold Time After /CS High /CS High to Power-down Mode /CS High to Standby Mode without Electronic Signature Read /CS High to Standby Mode with Electronic Signature Read /CS High to next Instruction after Suspend Write Status Register Time Byte Program Time (First Byte) (5) Additional Byte Program Time (After First Byte) (5) Page Program Time Sector Erase Time (4KB) Block Erase Time (32KB) Block Erase Time (64KB) Chip Erase Time W25Q80 Chip Erase Time W25Q16 Chip Erase Time W25Q32 Notes: 1. 2. 3. 4. 5. tCHHH tHHCH tCHHL tHHQX(2) tHLQZ(2) tWHSL(3) tSHWL(3) tDP(2) tRES1(2) tRES2(2) tSUS(2) tW tBP1 tBP2 tPP tSE tBE1 tBE2 tCE tLZ tHZ 5 5 5 7 12 20 100 3 3 1.8 20 10 30 6 1.5 120 0.5 0.75 12 25 50 15 50 12 3 200 1 1.5 25 40 80 ns ns ns ns ns ns ns s s s s ms s s ms ms s s s s s Clock high + Clock low must be less than or equal to 1/fC. Value guaranteed by design and/or characterization, not 100% tested in production. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1. Commercial temperature only applies to Fast Read (FR0 & FR1). Industrial temperature applies to all other parameters. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes programmed. - 51 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 11.9 Serial Output Timing 11.10 Input Timing 11.11 Hold Timing - 52 - www..com W25Q80, W25Q16, W25Q32 12. PACKAGE SPECIFICATION 12.1 8-Pin SOIC 208-mil (Package Code SS) SYMBOL MILLIMETERS MIN MAX INCHES MIN MAX A A1 A2 b C D E E1 e L y 1.75 2.16 0.05 0.25 1.70 1.91 0.35 0.48 0.19 0.25 5.18 5.38 7.70 8.10 5.18 5.38 1.27 BSC 0.50 0.80 0o 8o --0.10 0.069 0.085 0.002 0.010 0.067 0.075 0.014 0.019 0.007 0.010 0.204 0.212 0.303 0.319 0.204 0.212 0.050 BSC 0.020 0.031 0o 8o --0.004 Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within .0004 inches at the seating plane. - 53 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 12.2 8-Pin PDIP 300-mil (Package Code DA) D 8 5 E1 1 B B 1 4 S A A2 L e1 E c A1 Base Plane Seating Plane eA Symbol Dimension in inch Dimension in mm Min 0.010 0.125 0.016 0.058 0.008 Nom Max 0.175 Min 0.25 Nom Max 4.45 A A1 A2 B B1 c D E E1 e1 L 0.130 0.018 0.060 0.010 0.360 0.135 0.022 0.064 0.014 0.380 0.310 0.255 0.110 0.140 15 3.18 0.41 1.47 0.20 3.30 0.46 1.52 0.25 9.14 3.43 0.56 1.63 0.36 9.65 7.87 6.48 2.79 3.56 15 0.290 0.245 0.090 0.120 0 0.335 0.300 0.250 0.100 0.130 7.37 6.22 2.29 3.05 0 8.51 7.62 6.35 2.54 3.30 eA S 0.355 0.375 0.045 9.02 9.53 1.14 - 54 - www..com W25Q80, W25Q16, W25Q32 12.3 8-contact 6x5 WSON (Package Code ZP) - 55 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 12.4 8-contact 6x5 WSON Cont'd. - 56 - www..com W25Q80, W25Q16, W25Q32 12.5 16-Pin SOIC 300-mil (Package Code SF) SYMBOL MILLIMETERS MIN MAX INCHES MIN MAX A A1 b C D (3) 2.36 0.10 0.33 0.18 10.08 10.01 7.39 0.39 0 o 2.64 0.30 0.51 0.28 10.49 10.64 7.59 1.27 8 o 0.093 0.004 0.013 0.007 0.397 0.394 0.291 0.015 0 o 0.104 0.012 0.020 0.011 0.413 0.419 0.299 0.050 8o 0.003 E E1 e (3) (2) 1.27 BSC 0.050 BSC L y --- 0.076 --- Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. - 57 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 13. ORDERING INFORMATION (1) Notes: 1a. Only the 2 letter is used for the part marking. 1b. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T), when placing orders. 1c. The "W" prefix is not included on the part marking. nd - 58 - www..com W25Q80, W25Q16, W25Q32 13.1 Valid Part Numbers and Top Side Marking The following table provides the valid part numbers for the 25Q80/16/32 SpiFlash Memories. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 11-digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 9-digit number. PACKAGE TYPE SS SOIC-8 208mil SF SOIC-16 300mil ZP WSON-8 6x5mm DENSITY 8M-bit 16M-bit 32M-bit 16M-bit 32M-bit 8M-bit 16M-bit PRODUCT NUMBER W25Q80VSSIG W25Q16VSSIG W25Q32VSSIG W25Q16VSFIG W25Q32VSFIG W25Q80VZPIG W25Q16VZPIG TOP SIDE MARKING 25Q80VSIG 25Q16VSIG 25Q32VSIG 25Q16VFIG 25Q32VFIG 25Q80VPIG 25Q16VPIG - 59 - Publication Release Date: September 26, 2007 Preliminary - Revision B www..com W25Q80, W25Q16, W25Q32 14. A A1 REVISION HISTORY DATE PAGE DESCRIPTION VERSION 10/20/06 11/9/06 Various New Create Advanced Figures 2, 3A-B, 13A-14C, 16, 24, 25 Table 10.2.2: Write Status Reg 1 and 2 Erase Suspend 10.2.21 tCHSH, tSHCH = 5nS tSHSL = 10ns for Read & 50ns for Write, Erase and Program instructions Removed Burst Read Quad I/O Instruction. Updated ordering Information. Added transient voltage specification. Added Mode Bit Reset instruction and description. Added note for SRP1,0 status during Power LockDown protection. Updated Status Register memory protection tables. Updated Instruction Diagrams. Updated Status Register memory protection tables. Added note for Power Lock-Down, OTP functions. Added note for 64 Bit unique ID. Added note for 32KB/64KB block erase command. Updated Mode Bit Reset command description. Updated data retention temperature. Updated tSHSL description, added tCLQV2. Updated tBP1. A2 A3 A4 A5 11/15/06 2/22/07 4/20/07 6/20/07 49 20, 45, 49 & 57 19, 28, 30 & 45 13, 15-17 & 23 B 9/26/07 5, 11, 13, 15-17, 19, 35, 36, 43, 45-47, 50 & 59 Preliminary Designation The "Preliminary" designation on a Winbond SpiFlash memory datasheet indicates that the product is not fully characterized. The specifications are subject to change and are not guaranteed. Winbond or an authorized sales representative should be consulted for current information before using this product. Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. - 60 - www..com W25Q80, W25Q16, W25Q32 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 61 - Publication Release Date: September 26, 2007 Preliminary - Revision B |
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